Modern processors, especially in microcomputers built into equipment, utilize a system with a one chip processor made up of a CPU for general processing tasks and a multiple peripheral IP for special processing tasks all mounted on a single chip. This type of system typically has a structure where multiple devices, such as the CPU and the peripheral IP, are connected to a bus within a processor. These types of systems, in particular, contain multiple bus master devices for issuing access requests to the bus.
The bus master device in a processor containing a CPU sometimes accesses the bus unintentionally due to: (1) software bugs, (2) hardware bugs, and (3) temporary hardware problems (such as software errors on the α line). This type of access is called illegal address accessing. Product defects due to software bugs caused by illegal address accessing are especially numerous in built-in equipment applications.
To illustrate those cases in an application of the present invention where illegal address accessing has occurred, an example will be considered here which involves a system with multiple bus masters for image input and processing. The system structure is shown in FIG. 10. Here, the reference numeral 810 denotes the image input section and numeral 830 denotes the memory. The image input section 810 and the memory 830 are both connected to the system bus 800. The image input section 810, for example, loads images from a camera and stores that data in the memory 830 by operating a bus master. The numeral 850 indicates the flow of data during that operation.
The reference numeral 820 denotes the image processor section for performing color correction and noise elimination. The image processor section 820 loads image data from the memory 830 and writes back the processing results. The numerals 851 and 852 respectively indicate the flow of data.
The memory writing 850 from the image input section 810, and the memory writing 852 from the image processor section 820 must be performed in parallel. Therefore, switching must be performed to prevent conflicts arising from both accesses (850 and 852) to the memory area (at the same time).
FIG. 11 is a memory map of the system shown in FIG. 10. The section shown in area 910 is the area for the memory 830. In order to operate the image input section 810 and the image processor section 820 in parallel and avoid conflicts in the memory area, the image input section 810 must write in area 921 of area 910 and the image processor section 820 must write in area 920 thereof within a time period T. In the same way, the respective areas 922 and 921 must be written in T+1, and the areas 920 and 922 must be written in T+2.
The above-mentioned memory area switching which is employed to avoid conflicts in the memory area is especially important in systems having multiple bus masters. When conflicts in the memory area occur, for example, due to control software bugs, the problem occurs that image data cannot be processed correctly.
The CPU core typifying the bus master device contains a device called the MMU (Memory Management Unit). The MMU both detects and blocks illegal address accessing. However, the peripheral IP generally does not contain an MMU. A typical MMU used here with a peripheral IP also converts virtual addresses within the CPU core into actual addresses so that using the MMU for blocking illegal address accessing requires a large overhead in terms of the number of circuits and the software overhead to handle these circuits. The MMU therefore cannot be used for detecting and blocking illegal address accessing from a peripheral IP.